1. Technical Field
A well structure in a high voltage device is disclosed which is capable of improving a well breakdown voltage (BVDSS) and preventing charge-up and latch-up at a substrate in the high voltage device used in a flash memory.
2. Discussion of the Related Art
In general, the flash memory is mainly classified into an NOR type and a NAND type depending on a shape in which memory cells are connected to bit lines. A high voltage is used in the NAND type flash memory or the NOR type flash memory in order to perform a program operation or an erase operation. In order for the NAND type flash memory to perform the program operation or the erase operation, a voltage of about 20V is required. Further, in order for the NOR type flash memory to perform the program operation or the erase operation, a voltage of about 14V is needed. In order to apply such high voltage to a cell region, a high voltage device is located in a peripheral circuit region.
In case of the NAND type flash memory, upon the program operation and the erase operation, a high voltage of about 20V is used as described above. Such a high voltage is obtained through a high voltage device. The high voltage device has a PMOS transistor and a native transistor within the N-well. As the N-well and N+ pickup are applied a high voltage, it is required that the well breakdown voltage of the N-well itself be about 30V. In other words, upon the program operation and the erase operation of the NAND type flash memory, in order for the high voltage device to stably apply the high voltage to the cell transistor, it is required that the well breakdown voltage of the high voltage device be 30V or higher. Even in case of the NOR type flash memory, it may well have a high well breakdown voltage even though its value may be different from that of the NAND type flash memory.
FIG. 1 is a cross-sectional view illustrating a basic well structure in a conventional high voltage device. In order to have a high well breakdown voltage, an N-well 12 is formed in a P type substrate 11 and a P-well 13 spaced apart from the N-well 12 by a given distance is formed in the P type substrate 11. In case of a structure in which the N-well 12 and the P-well 13 contact each other, the well breakdown voltage is about 18V. The high voltage device of this well structure could not be applied to devices that require the well breakdown voltage of 18V or higher, for example, the NAND type flash memory. Therefore, in case of the NAND type flash memory, the N-well 12 is separated by a distance of 20 μm or greater from the P-well 13 when it is formed in the P type substrate 11. In more detail, in the N-well 12 within the P type substrate 11, a lateral diffusion becomes about 1 μm, the depletion region is abruptly formed at a low voltage and the depletion region is not increased at a voltage of over a given value, i.e., due to a high resistance of the P type substrate 11. For this reason, a breakdown voltage of 40V or higher is kept at a distance of 20 μm or greater. As such, in case of the NAND flash memory, there occurs a problem where the high voltage device is formed by making the distance between the N-well 12 and the P-well 13 20 μm or greater. As the density of the NAND type flash memory recently becomes higher, it is required that the distance between the N-well 12 and the P-well 13 be narrowed. In order to solve this problem, in the NAND type flash memory of 0.12 μm level, field stop implant region 14 using boron is formed in the P type substrate 11 between the N-well 12 and the P-well 13. From a simulation shown in FIG. 3, however, it can be seen that the well breakdown voltage is low, about 23V, when the N-well 12 and the field stop implant region 14 are connected (0.0 μm). In FIG. 1, an unexplained reference numeral 15 indicates a field oxide film.
As described above, the conventional well structure in the high voltage device has limitations in higher-integration of the flash memory or the semiconductor device that requires the high well breakdown voltage.